1. Technical Field
Various embodiments of the inventive concept generally relate to an analog capacitor of a semiconductor device, and more particularly to an analog capacitor of a semiconductor device capable of preventing output voltage variation due to parasitic capacitance.
2. Related Art
In general, analog capacitors may be formed in a peripheral circuit region of a semiconductor device together with logic circuits. In a complementary metal oxide semiconductor (CMOS) logic structure, the analog capacitors may have a metal-insulator-metal (MIM) structure.
The MIM analog capacitor may include a first metal layer, a dielectric layer, and a second metal layer. When these layers are formed, metal interconnect wires may be formed over the peripheral circuit region in which integrated circuits are located. This type of MIM analog capacitor, however, requires a separate process step to form the dielectric layer.
The analog capacitor may also be formed using a single metal layer.
The analog capacitor formed of the single metal layer may also be located over the peripheral circuit region in which peripheral circuits are formed, and this type of analog capacitor may be formed by placing a dielectric material between metals located on the same plane as the dielectric material.
However, since the analog capacitor formed of the single metal layer is located near the peripheral circuit region, the analog capacitor may be affected by noise. As a result, parasitic capacitances may induce noise in an output voltage of the analog capacitor.